1. Field
The embodiments described herein relate to an electrically rewritable non-volatile semiconductor memory device.
2. Description of the Related Art
NAND type flash memories are known as electrically rewritable semiconductor memory devices that are capable of a high degree of integration. In a NAND type flash memory, a NAND cell unit is configured by a plurality of memory cells that are connected in series such that a source diffusion layer of one memory cell is shared as a drain diffusion layer of its adjoining memory cell. Both ends of the NAND cell unit are connected to a bit line and a source line respectively through select gate transistors. Such a configuration of the NAND cell unit realizes a smaller unit cell area and a larger memory capacity than those realized in a NOR type memory.
A memory cell of a NAND type flash memory includes a charge accumulation layer (a floating gate electrode) formed above a semiconductor substrate via a tunnel insulating film, and a control gate electrode stacked above the charge accumulation layer via an inter-gate insulating film. The memory cell stores data in a nonvolatile manner according to a charge accumulation state of the floating gate electrode. For example, the memory cell executes binary data storage in which a high threshold voltage state with charges injected in the floating gate electrode is represented by data “0” and a low threshold voltage state with charges discharged from the floating gate electrode is represented by data “1”. Recent memory cells also store multi-value data such as four-value data, eight-value data, and so on, by subdividing the threshold voltage distributions to be written.
A data erase operation of the NAND type flash memory is performed on a block basis. The data erase operation is performed by setting all word lines in the selected block to 0 V, and applying the p-type well in which a memory cell array is formed with a boosted positive erase voltage (for example, 18 V to 20 V). A negative threshold voltage state (an erased state) is thus provided in which charges of the floating gate electrodes are discharged in all memory cells in the selected block. Further, in the data erase of the NAND type flash memory, a verify read (an erase verify operation) may be performed to determine whether the erased state is provided. If the erase verify operation determines that the erase is insufficiently performed, the erase voltage is stepwise raised (stepped up) and the same erase operation and erase verify operation are repeated.
A scheme is known that performs the so-called soft-programming operation to eliminate the over-erased state of the memory cell after the batch erase operation. The soft-programming operation can decrease the width of the threshold voltage distribution after the erase operation. Thus, in the subsequent write operation, the desired threshold voltage can be accurately written in the memory cell.
Repeated write/erase operations on the memory cell result in a degraded tunnel insulating film. When the erase operation and the soft-programming operation are performed without consideration of the memory cell degradation, the erase operation and the soft-programming operation may not be accurately performed in the memory cell.